This article discusses various ways that makefiles can be used
other than just to build software. A makefile can be used to
group commands into a single file. Groups of commands can be
given within a target, and can depend on other commands by
depending on other targets.
Common setup
I use the following common setup at the top of most of my makefiles.
Non-recursive make.
I don't really like using recursive make when I can avoid it. I have
a utility script that I can use with GNU make that helps to set up the
variables at the top of a makefile. Then, instead of recursing into
a makefile, I use the macros to include the file. Within an included
file I call another macro at the very top in order to obtain the file
and directory of that makefile (which may be relative to the top
makefile directory).
This defines the following macros.
PUSH
This macro will push the value of a variable onto a stack.
POP
This macro will pop the value of the top of the stack into a variable.
SUBINCLUDE
This will include the files specified and set __FILE__.
Inside a makefile, it is possible to define local variables and macros by
suffixing them. Since the values of variables may change outside, the
immediate assignment (:=) should be used for variables. For any rules that use
the variables, target specific variables should be assigned so the rule uses the
correct values. Dependencies are handled correctly since they are evaluated
when they are encounted.